Settling Time of Mesochronous Clock Retiming Circuits for Low Swing Interconnects

It is well known that timing jitter can degrade the bit error rate (BER) of receivers that recover clock information from the input data. However, timing jitter can also result in an indefinite increase in the settling time of clock recovery circuits at the receivers, particularly in low swing mesochronous systems. Mesochronous clock retiming circuits are required in repeaterless low swing on-chip interconnects in order to sample the low swing data at the center of the eye. This paper discusses the settling time of these circuits. First, a discussion on how timing jitter can result in large increase in the settling time of the clock recovery circuit is presented. Next, the circuit is modeled as a Markov chain with absorbing states. Here, the mean time of absorption of the Markov chain, which represents the mean settling time of the circuit, is determined. The model is validated by using behavioural simulations of the circuit, the results of which match well with the model predictions. The modelling is applied to study the effect of different types of jitter, like data dependent jitter of 1 bit and 2 bits, random jitter and random jitter along with 1 bit data dependent jitter. Finally, a few techniques of reducing the settling time are presented and their efficacy is confirmed with circuit simulations.